ez-usb nx2lp? usb 2.0 nand flash controller cy7c68023/cy7c68024 cypress semiconductor corporation 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-08055 rev. *a revised march 16, 2005 1.0 features high (480-mbps) or full (12-mbps) speed usb support both common nand page sizes supported ? 512bytes ?up to 1gbit capacity ? 2k bytes ?up to 8gbit capacity 8 chip enable pins ? up to 8 nand flash single-device chips ? up to 4 nand flash dual-device chips industry standard ecc nand flash correction ? 1-bit per 256 correction ? 2-bit error detection industry standard (smartmedia) page management for wear leveling algorithm, bad block handling, and physical to logical management. supports 8-bit nand flash interfaces supports 30ns, 50ns, 100ns nand flash timing complies with usb mass storage class specification rev 1.0 cy7c68024 complies with usb 2.0 specification for bus- powered devices (tid# 40460274) 43-ma typical active current space-saving and lead-free 56-qfn package (8mm 8mm) support for board-level manufacturing test via usb interface 3.3v nand flash operation ? nand flash power management support 2.0 introduction the ez-usb nx2lp ? ( nx2lp ) implements a usb 2.0 nand flash controller. this controller adheres to the mass storage class bulk-only transport specification . the usb port of the nx2lp is connected to a host computer directly or via the downstream port of a usb hub. host software issues commands and data to the nx2lp and receives status and data from the nx2lp using standard usb protocol. the nx2lp supports industry leading 8-bit nand flash inter- faces and both common nand page sizes of 512 and 2k bytes. eight chip enable pins allow the nx2lp to be connected to up to eight single- or four dual-device nand flash chips. certain nx2lp features are configurable, enabling the nx2lp to meet the needs of different designs? requirements. figure 1-1. nx2lp block diagram usb 2.0 xceiver smart hs/ fs usb engine nand flash interface logic 8-bit data bus nand control signals ez-usb nx2lp internal control logic pll 24 mhz xtal vbus d+ d- data control chip reset led1# led2# write protect chip enable signals
cy7c68023/cy7c68024 document #: 38-08055 rev. *a page2of9 3.0 pin assignments 3.1 pin diagram figure 3-1. 56-pin qfn 3.2 pin descriptions pin name type default state at start-up description 1 r_b1# [1] i z ready/busy 1 (2.2k to 4k pull-up resistor is required) 2 r_b2# i z ready/busy 2 (2.2k to 4k pull-up resistor is required) 3 avcc pwr pwr analog 3.3v supply 4 xtalout xtal n/a crystal output 5 xtalin xtal n/a crystal input 6 agnd gnd gnd ground 7 avcc pwr pwr analog 3.3v supply 8 dplus i/o z usb d+ 9 dminus i/o z usb d- 10 agnd gnd gnd ground 11 vcc pwr pwr 3.3v supply 12 gnd gnd gnd ground 13 n/c n/a n/a no connect 14 gnd gnd gnd ground note: 1. a # sign after the pin name indicates that it is an active low signal. reset# gnd n/c n/c wp_sw# wp_nf# led2# led1# ale cle vcc re1# re0# we# r_b1# r_b2# avcc xtalout xtalin agnd avcc dplus dminus agnd vcc gnd n/c gnd 15 16 17 18 19 20 21 22 23 24 25 26 27 28 reserved reserved vcc dd0 dd1 dd2 dd3 dd4 dd5 dd6 dd7 gnd vcc gnd 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 gnd vcc n/c gnd ce7# ce6# ce5# ce4# ce3# ce2# ce1# ce0# reserved vcc ez-usb nx2lp 56-pin qfn
cy7c68023/cy7c68024 document #: 38-08055 rev. *a page3of9 15 reserved n/a n/a must be tied high (no pull-up resistor required) 16 reserved n/a n/a must be tied high (no pull-up resistor required) 17 vcc pwr pwr 3.3v supply 18 ddo i/o z data 0 19 dd1 i/o z data 1 20 dd2 i/o z data 2 21 dd3 i/o z data 3 22 dd4 i/o z data 4 23 dd5 i/o z data 5 24 dd6 i/o z data 6 25 dd7 i/o z data 7 26 gnd gnd gnd ground 27 vcc pwr pwr 3.3v supply 28 gnd gnd gnd ground 29 we# o h write enable 30 re0# o h read enable 0 31 re1# o h read enable 1 32 vcc pwr pwr 3.3v supply 33 cle o z command latch enable 34 ale o z address latch enable 35 led1# o z data activity led sink 36 led2# o z chip active led sink 37 wp_nf# o z write-protect nand flash 38 wp_sw# i z write-protect switch input 39 n/c n/a n/a no connect 40 n/c n/a n/a no connect 41 gnd gnd gnd ground 42 reset# i z nx2lp chip reset 43 vcc pwr pwr 3.3v supply 44 reserved n/a n/a must be tied high 45 ce0# o z chip enable 0 46 ce1# o z chip enable 1 47 ce2# o z chip enable 2 48 ce3# o z chip enable 3 49 ce4# o z chip enable 4 50 ce5# o z chip enable 5 51 ce6# o z chip enable 6 52 ce7# o z chip enable 7 53 gnd gnd gnd ground 54 n/c n/a n/a no connect 55 vcc pwr pwr 3.3v supply 56 gnd gnd gnd ground 3.2 pin descriptions (continued) pin name type default state at start-up description
cy7c68023/cy7c68024 document #: 38-08055 rev. *a page4of9 3.3 additional pin descriptions 3.3.1 dplus, dminus dplus and dminus are the usb signaling pins, and they should be tied to the d+ and d? pins of the usb connector. because they operate at high frequencies, the usb signals require special consideration when designing the layout of the pcb. general guidelines are given at the end of this document. 3.3.2 xtalin, xtalout the nx2lp requires a 24-mhz ( 100ppm) signal to derive internal timing. typically, a 24-mhz (20-pf, 500-uw, parallel- resonant fundamental mode) crystal is used, but a 24-mhz square wave from another source can also be used. if a crystal is used, connect its pins to xtalin and xtalout, and also through 12-pf capacitors to gnd. if an alternate clock source is used, apply it to xtalin and leave xtalout open. 3.3.3 data[7-0] the data[7-0] i/o pins provide an 8-bit interface to a nand flash device. these pins are used to transfer address, command, and read/write data between the nx2lp and nand flash. 3.3.4 r_b[2-1]# the ready/busy input pins are used to determine the state of the currently selected nand flash device. these pins must be pulled high through a 2k-4k resistor. these pins are pulled low by the nand flash when it is busy. 3.3.5 we# the write enable output pin is used by the nand flash to latch commands, address, and data during the rising edge of the pulse. 3.3.6 re[1-0]# the read enable output pins are used to control the data flow from the nand flash devices. the device presents valid data and will increment its internal column address counter by one step on each falling edge of the read enable pulse. a 10k pull- up is an option for re1-0#. 3.3.7 cle the command latch enable output pin is used to indicate that the data on the i/o bus is a command. the data is latched into the nand flash control register on the rising edge of we# when cle is high. 3.3.8 ale the address latch enable output pin is used to indicate that the data on the i/o bus is an address. the data is latched into the nand flash address register on the rising edge of we# when ale is high. 3.3.9 led1# the data activity led output pin is used to indicate data transfer activity. led1# is asserted low at the beginning of a data transfer, and set to a high-z state when the transfer is complete. if this functionality is not utilized, leave led1# floating. 3.3.10 led2# thechipactiveledoutputpinisusedtoindicateproper device operation. led2# is asserted low when the nx2lp is powered and initialized. it is placed in a high-z state under all other conditions. if this functionality is not utilized, leave led2# floating. 3.3.11 wp_nf# the write-protect nand flash output pin is used to control the write-protect pins on nand flash devices. this pin should be tied to the write protect pins of the nand flash devices. if wp_sw# is asserted low during a data transfer, or if internal operations are still pending, the nx2lp will wait until the operation is complete before asserting wp_nf# to ensure that there is no data loss or risk of os error. 3.3.12 wp_sw# the write-protect switch input pin is used to select whether or not nand flash write-protection is enabled by the nx2lp. when the pin is asserted low, the nx2lp will report to the host that the nand flash is write-protected, the wp_nf# will be driven low, and any attempts to write to the configuration data memory area will be blocked by the nx2lp. if this pin is asserted low during a data transfer, or if internal operations are still pending, the nx2lp will wait until the operation is complete before asserting wp_nf# to ensure that there is no data loss or risk of os error. 3.3.13 ce[7-0]# the chip enable output pins are used to select the nand flash that the nx2lp will interface. unused chip enable pins should be left floating. 3.3.14 reset# asserting reset# for 10 ms will reset the nx2lp. a reset and/or watchdog chip is recommended to ensure that startup and brownout conditions are properly handled. figure 3-2. xtalin, xtalout diagram 24mhz xtal 12pf xtalin xtalout 12pf 12pf capacitor values assume a trace capacitance of 3pf per side on a four-layer fr4 pcb
cy7c68023/cy7c68024 document #: 38-08055 rev. *a page5of9 4.0 applications the nx2lp is a high-speed usb 2.0 peripheral device that connects nand flash devices to a usb host using the usb mass storage class protocol. 4.1 additional resources CY3685 ez-usb nx2lp development kit cy4618ez-usbnx2lpreferencedesignkit usb specification version 2.0 usb mass storage class bulk only transport specification , http://www.usb.org/developers/data/devclass/ usbmassbulk_10.pdf. 5.0 functional overview 5.1 usb signaling speed the nx2lp operates at two of the three rates defined in the usb specification revision 2.0 dated april 27, 2000: full speed, with a signaling bit rate of 12 mbits/sec high speed, with a signaling bit rate of 480 mbits/sec. the nx2lp does not support the low-speed signaling rate of 1.5 mbits/sec. 5.2 nand flash interface during normal operation the nx2lp supports an 8-bit i/o interface, eight chip enable pins, and other control signals compatible with industry standard nand flash devices. 6.0 enumeration during the start-up sequence, internal logic checks for the presence of nand flash with valid configuration data in the configuration data memory area. if valid configuration data is found, the nx2lp uses the values stored in nand flash to configure the usb descriptors for normal operation as a usb mass storage device. if no nand flash is detected, or if no valid configuration data is found in the configuration data memory area, the nx2lp uses the default values from internal rom space for manufacturing mode operation. the two modes of operation are described in sections 6.1 and 6.2 below. 6.1 normal operation mode in normal operation mode, the nx2lp behaves as a usb 2.0 mass storage class nand flash controller. this includes all typical usb device states (powered, configured, etc.). the usb descriptors are returned according to the data stored in the configuration data memory area. normal read and write access to the nand flash is available in this mode. 6.2 manufacturing mode in manufacturing mode, the nx2lp enumerates using the default descriptors and configuration data that are stored in internal rom. this mode allows for first-time programming of the configuration data memory area, as well as board-level manufacturing tests. a unique usb serial number is required for each device in order to comply with the usb mass storage specification. also, cypress requires designers to use their own vendor id for final products. the vendor id is obtained through regis- tration with the usb implementor?s forum (usb-if), and the product id is determined by the designer. cypress provides all the software tools and drivers necessary for properly programming and testing the nx2lp. please refer to the documentation in the development or reference design kit for more information on these topics. nand flash programmed? load default descriptors and configuration data manufacturing mode load custom descriptors and configuration data enumerate as usb mass storage device normal operation mode start-up enumerate as generic nx2lp device nand flash present? no yes yes no figure 6-1. nx2lp enumeration process
cy7c68023/cy7c68024 document #: 38-08055 rev. *a page6of9 6.3 configuration data certain features in the nx2lp can be configured by the designer to disable unneeded features, and to comply with the usb 2.0 specification?s descriptor requirements for mass storage devices. table 6-1 lists the variable configuration data and the default values that are stored in internal rom space. the default rom values are returned by an unprogrammed nx2lp device. 7.0 design notes for the quad flat no lead (qfn) package the nx2lp comes in a 56-pin qfn package, which utilizes a metal pad on the bottom to aid in heat dissipation. the low- power operation of the nx2lp makes the thermal pad on the bottom of the qfn package unnecessary. because of this, pcb layout may utilize the space under the nx2lp for routing signals as needed, provided that any traces or vias under the thermal pad are covered by solder mask or other material to prevent shorting. standard pcb layout recommendations for usb devices still apply. for further information on this package design, please refer to the application note from amkor titled ?surface mount assembly of amkor?s microleadframe (mlf) technology.? this application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc. 8.0 pcb layout recommendations the following recommendations should be followed to ensure reliable high-speed usb performance operation. a four-layer impedance controlled board is recommended to ensure best signal quality. specify impedance targets (ask your board vendor what they can achieve). maintain trace widths and trace spacing to control imped- ance. minimize stubs on dplus and dminus to avoid reflected signals. place any connections between the usb connector shell and signal ground near the usb connector. use bypass/flyback caps on vbus, placed near connector. keep dplus and dminus trace lengths to within 2 mm of each other in length, with preferred length of 20?30 mm. maintain a solid ground plane under the dplus and dmi- nus traces. do not allow the plane to be split under these traces. place no vias on the dplus or dminus trace routing. isolate the dplus and dminus traces from all other signal traces (use >10 mm. spacing for best signal quality). source for recommendations: ez-usb fx2 pcb design recommendations, www.cy- press.com/cfuploads/support/app_notes/fx2_pcb.pdf. high-speed usb platform design guidelines, www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf. 9.0 absolute maximum ratings storage temperature ................................... ?65c to +150c ambient temperature with power supplied ............................................................ 0c to +70c supply voltage to ground potential ...............?0.5v to +4.0v dc input voltage to any input pin ................................ 5.25v dc voltage applied to outputs in high-z state..................................... ?0.5v to vcc + 0.5v power dissipation..................................................... 300 mw static discharge voltage.............................................. 2000v max output current per io port................................... 10 ma 10.0 operating conditions [2] t a (ambient temperature under bias) ............. 0c to +70c supply voltage ...........................................+3.15v to +3.45v ground voltage ................................................................. 0v f osc (oscillator or crystal frequency) ... 24 mhz 100 ppm .................................................................. parallel resonant note: 2. if an alternate clock source is input on xtalin, it must be supplied with standard 3.3v signaling characteristics and xtalout must be left floating. table 6-1. variable configuration data and default rom values configuration data description default rom value vendor id usb vendor id (assigned by usb-if) 0x04b4 (cypress) product id usb product id (assigned by designer) 0x6813 serial number usb serial number n/a manufacturer string manufacturer string in usb descriptors n/a product string product string in usb descriptors n/a enable write protection enables write protection capability enabled scsi device name string shown in the device manager properties n/a
cy7c68023/cy7c68024 document #: 38-08055 rev. *a page7of9 12.0 ac electrical characteristics 12.1 usb transceiver the nx2lp?s usb interface complies with the usb 2.0 speci- fication for bus-powered devices. 12.2 nand flash timing the nx2lp supports 30ns, 50ns and 100ns nand flash devices. 13.0 ordering information note: 3. measured at max vcc, 25 c. 11.0 dc characteristics parameter description conditions min. typ. max. unit v cc supply voltage 3.15 3.3 3.45 v v cc ramp supply ramp-up 0v to 3.3v 200 s v ih input high voltage 2 5.25 v v il input low voltage ?0.5 0.8 v i i input leakage current 0 < v in 3.0v 5.0 ms pin reset after valid startup 200 s part number package type cy7c68023-56lfxc 56-pin qfn lead-free for self/bus power cy7c68024-56lfxc 56-pin qfn lead-free for battery power CY3685 ez-usb nx2lp development kit cy4618 ez-usb nx2lp reference design kit
cy7c68023/cy7c68024 document #: 38-08055 rev. *a page 8 of 9 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semiconductor corporati on assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress produ cts are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant in jury to the user. the inclusion of cypress 14.0 package diagram 15.0 disclaimers, trademarks, and copyrights ez-usb nx2lp is a trademark, and ez-usb is a registered trademark, of cypress semiconductor corporation. all product and company names mentioned in this document are the trademarks of their respective holders. figure14-1.56-leadquadflatpacknolead(8x8mm)lf56 0.80[0.031] 7.70[0.303] 7.90[0.311] a c 1.00[0.039] max. n seating plane n 2 0.18[0.007] 0.50[0.020] 1 1 0.08[0.003] 0.50[0.020] 0.05[0.002] max. 2 (4x) c 0.24[0.009] 0.20[0.008] ref. 0.80[0.031] max. pin1 id 0-12 6.45[0.254] 8.10[0.319] 7.80[0.307] 6.55[0.258] 0.45[0.018] 0.20[0.008] r. 8.10[0.319] 7.90[0.311] 7.80[0.307] 7.70[0.303] dia. 0.28[0.011] 0.30[0.012] 6.55[0.258] 6.45[0.254] 0.60[0.024] top view bottom view side view e-pad (pad size vary by device type) 51-85144-*d 56-lead qfn 8 x 8 mm lf56a dimensions in mm e-pad size 4.3 x 5.0 mm (typ.)
cy7c68023/cy7c68024 document #: 38-08055 rev. *a page9of9 document history page description title: cy7c68023/cy7c68024 ez-usb nx2lp? usb 2.0 nand flash controller document number: 38-08055 rev. ecn no. issue date orig. of change description of change ** 286009 see ecn gir new data sheet (preliminary information). *a 334796 see ecn gir adjusted default vid/pid; released as final.
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